The present invention relates to an emitter-coupled logic (to be referred to as an ECL hereinafter) synchronous logic circuit using bipolar transistors.
In an ECL synchronous logic circuit, the bipolar transistors arranged therein switch in an unsaturated state to achieve high-speed switching.
In a logic circuit such as a synchronous latch and a synchronous flip-flop used for synchronizing a given signal with a synchronizing signal, an input logic circuit is often arranged at a signal input terminal of the above-described latch or flip-flop so as to obtain a predetermined logic signal from a plurality of signals.
For example, as shown in a block diagram of FIG. 1, an input logic circuit 15 having AND gates 12 and 13 and an OR gate 14 is arranged to supply to an signal input terminal IN of a synchronous latch 11 one of logic signals A and B in accordance with the logic level of a selection signal C. The selected signal from the input logic circuit 15 is produced from output terminals D and D, respectively, of the latch 11 in response to a synchronizing signal supplied to a synchronizing signal input terminal CK of the latch 11. FIG. 2 is a block diagram of a conventional input logic circuit 15 having only an OR gate 16. The OR gate 16 receives two logic signals A and B. In order to synchronize an input signal with a synchronizing signal, a synchronous flip-flop may be used in place of the synchronous latch 11. In the conventional synchronous logic circuit having the input logic circuit at its signal input terminal, high-speed switching cannot be performed. In addition to this disadvantage, the number of circuit elements is great, and power consumption is high.